Operational amplifiers are a basic building block in electronic systems, and their performance broadly affects the overall performance of the systems in which they are embedded. The performance of operational amplifiers has been generally limited by the underlying characteristics of the transistors and other components with which they are built. Such component limitations directly affect the maximum bandwidth of the amplifier, its gain, and the efficiency with which it can amplify signals.
Substantial progress has been made in the development of new amplifier circuits for applications requiring high amplifier performance since the invention of the transistor in the late 1940s. The familiar textbook transistor voltage amplifier, using a resistor in series with the collector and a grounded emitter, has been substantially replaced by current-based configurations using a compensating transistor directly coupled to the base of an amplifying transistor to provide current feedback. This approach, which is also referred to as a translinear circuit or translinear loop, substantially improves linearity and provides inherent temperature compensation. This circuit and variations are described in B. Gilbert, “A New Wide-Band Amplifier Technique,” IEEE J. Solid State Circuits, Vol. SC-3, No. 4, December 1968, pp. 353-365, which is incorporated herein by reference. Translinear circuit elements are described by B. A. Minch, et al., “The Multiple-Input Translinear Element: A Versatile Circuit Element,” Proc. 1998 IEEE International Symposium on Circuits and Systems, Vol. 1, 31 May 1998, pp. 527-530, which is referenced and incorporated herein. Current mirrors are now also used to couple the output of one amplifying stage to the input of another without the need for frequency-limiting coupling capacitors as described in P. Horowitz, et al., “The Art of Electronics,” Cambridge Univ. Press, 2nd Ed., 1989, pp. 98-104, which is incorporated herein by reference. Low impedance circuit nodes associated with current amplification in present amplifiers substantially eliminate the otherwise unavoidable high-frequency poles associated with circuit parasitic capacitance and enable the design of amplifiers with bandwidths approaching the underlying transistor frequency ft, the frequency at which the current gain of a transistor falls to unity. Differential amplifiers provide input signal symmetry and are readily configured with paired transistors. Class AB input amplifiers achieve high efficiency by alternately conducting current with some current overlap through the two output transistors depending on the polarity of the input signal. Class AB amplifiers with sufficient feedback can still provide high levels of linearity and high gain, and can be arranged with further symmetry with respect to the bias supply by totem-pole circuits employing complementary transistor types. Such circuits are described, for example, by N. Gibson, et al. in U.S. Pat. No. 6,794,943, which is hereby referenced and incorporated herein. The overall result of these developments is circuits with amplifying bandwidth from dc to almost the ft of the constituent transistors, and with high levels of linearity. Stable amplification gains are thereby provided that are substantially independent of temperature but are dependent principally on the ratio of transistor areas.
Nonetheless, new applications for high bandwidth amplifiers continue to challenge previously obtainable results and present new needs for amplifiers with even better linearity while maintaining wide amplification bandwidth. High output drive capability and high gain are also often required. An example of such a need is for xDSL telephone circuits that accurately transmit high data-rate signals to modems on remote customer premises. A digital subscriber line, or DSL, can be configured in various arrangements, one of which is an asymmetric digital subscriber line, or ADSL, that transmits data at different rates depending on the direction of transmission; a generic descriptor for a DSL in one of various possible arrangements is “xDSL.” These xDSL applications utilize signals with frequency components exceeding 10 MHz and require minimal signal distortion for reliable data transmission. These applications also require the high amplification efficiency ordinarily associated with Class AB amplifiers to prevent overheating, but as the signal bandwidths continue to be extended beyond 10 MHz, the normal high efficiency of Class AB amplifiers is compromised by prior-art approaches that generally exhibit some level of current shoot-through in the last amplification stage that drives the output signal. This shoot-through results in power increase and degradation in linearity that can be at least proportional to the frequency of the signal being amplified. Thus, a new circuit approach is required to satisfy these applications without undue degradation in system performance, and that can use ordinary silicon components without introducing unnecessary power dissipation.
FIG. 1 shows a cascade circuit arrangement for a wide bandwidth amplifier of the prior art, illustrated generally as the amplifier 100, and is identified herein as Version 1. This circuit utilizes two cascade-coupled current-feedback amplifier stages driving a power output stage, and produces an output voltage VOUT from differential input voltage signals VIN+ and VIN−. The amplifier 100 typically operates as a Class AB amplifier to provide high amplification efficiency. The amplifier 100 is configured with a first current-feedback amplifier sub-circuit including the bipolar transistors Q1, Q2, Q3, and Q4 arranged as a generally symmetric differential current-feedback amplifier, and is supplied with constant and substantially equal currents from the current sources I1 and I2. The areas of transistors Q1, Q2, Q3, and Q4 are also generally equal. The transistors Q2 and Q4 can alternatively be configured as emitter followers as is well understood in the art. Current-feedback amplifiers are generally used in such applications because they can provide high slew rates, usually with good linearity, in response to high-frequency input signals. The current sources I1 and I2 are coupled respectively to the positive and negative bias rails VCC and VEE. Currents supplied by these current sources may be on the order of 0.1 mA, but other current levels can be used to meet the needs of a particular application.
The output currents from this non-symmetric input buffer subcircuit are reflected by current mirrors CM1 and CM2 to provide input currents for a second, current-feedback amplifier sub-circuit configured with bipolar transistors Q5, Q6, Q7, and Q8. The current mirrors CM1 and CM2 are usually configured with unity gain but can be arranged to provide current gain by altering the ratio of their constituent transistor areas as is well known in the art. The areas of transistors Q5, Q6, Q7, and Q8 are also usually equal. Transistors Q5 and Q7 are arranged in a diode-coupled circuit configuration to provide dc bias for transistors Q6 and Q8. A high-impedance node, node A, is formed at the junction of the emitters of transistors Q5 and Q7 and is by-passed to the negative bias rail VEE with compensation capacitor C1 to provide low impedance for signal components of interest and stable operation. The output currents from this second, current-feedback amplifier sub-circuit produced at the collectors of transistors Q6 and Q8 are reflected by current mirrors CM3 and CM4, also usually configured with unity gain, and are coupled to a unity gain buffer configured with bipolar transistors Q9, Q10, Q11, and Q12. The areas of transistors Q9, Q10, Q11, and Q12 are usually equal. Transistors Q9 and Q11 are arranged in a diode-coupled circuit configuration to provide dc bias for transistors Q10 and Q12. Transistors Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 constitute a buffered amplifier for the output signal VOUT. A high-impedance node is formed at node C, the junction of the emitters of transistors Q9 and Q11, and is by-passed to the negative bias rail VEE with compensation capacitor C2, again to provide a low impedance for signal components of interest and stable operation. The output node of this third sub-circuit is coupled to a further current mirror configured with bipolar transistors Q15 and Q16 and another current mirror configured with bipolar transistors Q13 and Q14 that are arranged to drive the output signal VOUT. The transistors Q14 and Q16 are large to support the high output-current driving ability of the amplifier, and are indicated on the figure as being N times larger than the transistors Q13 and Q15 where N can be substantially larger than unity and by and large is dependent on the system specifications. In practical terms, these ratios should be large enough to maintain low power dissipation and good linearity when driving heavy loads. Thus, the current mirrors configured with bipolar transistors Q15 and Q16 and transistors Q13 and Q14 have current gains of approximately N:1.
The output, VOUT, from the amplifier 100, is coupled through the resistor R1 to an inverting node, node B, of this cascaded amplifier arrangement to provide negative feedback to configure the gain of this portion of the amplifier 100. The current gain and stability of the amplifier 100 depend on the resistor R1.
A significant limitation of the circuit configuration illustrated in FIG. 1 is the high level of bias current that is drawn when amplifying signals with high-frequency components such as encountered in xDSL applications. This is a consequence of current “shoot through” resulting from the substantial collector-to-base junction capacitance of the large output transistors Q14 and Q16. When transistor Q16 is turned on by a high-frequency signal, the output voltage VOUT increases and an incremental current flows into node D due to the collector-to-base junction capacitance of transistor Q14. This current divides between the bases of transistors Q13 and Q14, but substantially all of the current flows into the base of transistor Q14 due to its larger area. The current moderately raises the voltage of node D because it is coupled to bases of two transistors with grounded emitters, and thereby briefly turns on transistor Q14 by the current that is caused to flow though the collector-to-base junction capacitance of transistor Q14 by the increasing voltage difference between its collector and base. Thus, a current shoot-through path is formed from the VCC bias rail to the VEE bias rail that can result in power dissipation for each cycle of the high-frequency signal being amplified. If the frequency components of the input signal are sufficiently high, the power dissipated is significant. A similar dissipative path is formed for current resulting from quickly varying voltage across the collector-to-base junction capacitance of transistor Q14 when the output voltage VOUT is rapidly decreasing. The voltage of node E is correspondingly reduced, briefly turning on transistor Q16 by the current that is caused to flow though the collector-to-base junction capacitance of transistor Q16 by the increasing voltage difference between its collector and base. Again, shoot-through results for each cycle of the high-frequency signal. Thus, substantial power is dissipated by the circuit in FIG. 1 when amplifying signals with high-frequency components, particularly above 10 MHz such as for xDSL type signals. The power dissipation is a consequence of the totem-pole arrangement of the output portion of the amplifier and the uncompensated collector-to-base capacitance of the output transistors with collectors coupled in series and to the output. Such high power dissipation results in low amplifier efficiency and even component damage if sufficient heat-sinking arrangements are not provided for the power-dissipating circuit elements. Although this circuit can be configured with high voltage gain, it also does not provide sufficient amplification linearity for high performance xDSL applications.
FIG. 2 shows another cascade arrangement of two current-feedback amplifier stages of the prior art, illustrated generally as the amplifier 200, and identified herein as version 2. Amplifier 200 also utilizes two cascade-coupled current-feedback amplifier stages driving a power output stage to produce an output voltage VOUT from a differential input signal VIN+ and VIN−. This second version can provide better amplification linearity than the first version illustrated in FIG. 1, but exhibits even worse shoot-through and attendant lower efficiency than the circuit illustrated on FIG. 1, particularly when amplifying signals with frequency components greater than 10 MHz.
The amplifier 200 includes current sources I1 and I2 and transistors Q1, Q2 . . . Q8 that are similar to corresponding circuit elements on FIG. 1 with the same reference designations and will not be re-described in the interest of brevity. The current sources I3 and I4 replace the current mirrors CM3 and CM4 illustrated on FIG. 1 and typically provide equal currents to bias the collectors of transistors Q6 and Q8. These currents are not necessarily equal to the currents from current sources I1 and I2. The output current signals from transistors Q6 and Q8 are coupled to transistors Q19 and Q20 which are biased by bias sources BIASA and BIASB. These bias sources may be configured, for example, with translinear loops as illustrated and described below with reference to FIG. 3a to provide a stable dc operating point for transistors Q19 and Q20. Other bias schemes could be used. Transistors Q19 and Q20 are typically larger than transistors Q1, Q2 . . . Q8 to provide sufficient drive for the output stage. Capacitors C5 and C6 provide added Miller compensation for the second stage of the amplifier beyond that normally provided by the intrinsic collector-to-base capacitance of the transistors and are included to split high-frequency poles in the circuit for added stability. Transistors Q23 and Q25 provide linearized and temperature-corrected bias voltage for the output transistors Q24 and Q26. The area ratio of Q23 to Q24 is 1:M as indicated on the figure, where M is usually substantially greater than unity and by and large is determined by system requirements and process parameters. The area ratio of Q25 to Q26 is also 1:M. The resistor R2 injects a feedback current signal dependent on the output voltage VOUT into the node B, which is a low impedance signal-inverting node for the current feedback amplifier—stage 2. The resistor R2 is usually selected to provide unity gain for the current feedback amplifier—stage 2. The resistor R2 also affects circuit bandwidth and stability.
The amplifier 200 illustrated on FIG. 2 also exhibits shoot-through because Q19 and Q20 have substantial Miller compensation capacitance plus the parasitic collector-to-base capacitance that forms a dynamic current path for high-frequency signals that is in phase between the base of Q19 and the base of Q20. An unwanted increase in signal current is directly coupled to the output stage that in turn amplifies the current, producing a shoot-through current pulse. The output stage is configured with large-area transistors Q24 and Q26 that provide the further current pulse amplification. Thus, a current shoot-through path is formed from the VCC bias rail to the VEE bias rail that can result in significant power dissipation, and substantial power is dissipated by the circuit on FIG. 2, particularly when amplifying signals with frequency components above 10 MHz, again due to the totem-pole arrangement of the output portion of the amplifier and the uncompensated collector-to-base capacitance of the output transistors, this time with emitters coupled in series and to the output.
Thus, linear amplifiers employing circuits of the prior art have limited utility in xDSL and other wide bandwidth applications requiring high efficiency. Wide bandwidth signals ordinarily incur unnecessary power losses using totem-pole circuit configurations of the prior art due to current shoot-through, particularly when utilizing two transistors of substantial area and configured either with emitters or collectors coupled in series. A need thus exists for further improvement to these circuits to reduce or eliminate shoot-through without compromising circuit linearity, bandwidth, gain, or output drive capability.